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421	Point-to-Point Synchronisation on Shared Memory Architectures J. Mark Bull and Carwyn Ball EPCC, The King’s Buildings, The University of Edinburgh, Mayfield Road, Edinburgh EH9 3JZ, Scotland, U.K. email: Add to Reading List Source URL: www.compunity.org Language: English - Date: 2007-10-15 03:40:58 Computer programming OpenMP Barrier Thread Scheduling CPU cache Computing Concurrent computing Parallel computing
422	SPEC CINT2006 Result CopyrightStandard Performance Evaluation Corporation aws -- Add to Reading List Source URL: s3.amazonaws.com Language: English - Date: 2014-11-12 10:33:40 Computer hardware Evaluation Standard Performance Evaluation Corporation Benchmark Ubuntu Computer performance CPU cache Intel C++ Compiler Xeon Computing SPECint Computer architecture
423	SPEC CINT2006 Result CopyrightStandard Performance Evaluation Corporation rackspace -- Add to Reading List Source URL: s3.amazonaws.com Language: English - Date: 2015-03-24 08:58:47 Computer hardware Standard Performance Evaluation Corporation Rackspace CPU cache Benchmark Xeon Computing SPECint Evaluation
424	Prefetching and Cache Management Using Task Lifetimes Vassilis Papaefstathiou∗ Manolis G.H. Katevenis∗ FORTH-ICS Add to Reading List Source URL: www.ics.forth.gr Language: English - Date: 2014-02-26 04:38:59 Computer memory Cache Central processing unit Microprocessors CPU cache Prefetcher Multi-core processor Microarchitecture X86 Computer hardware Computing Computer architecture
425	NFES SUPPLIES REQUEST Version 1.2 Incident Name: Incident Number: Person Requesting: Add to Reading List Source URL: gacc.nifc.gov Language: English - Date: 2014-06-20 16:19:43 CPU cache Cache Central processing unit Computer memory
426	SPEC CINT2006 Result CopyrightStandard Performance Evaluation Corporation aws -- Add to Reading List Source URL: s3.amazonaws.com Language: English - Date: 2015-04-16 09:29:56 Evaluation Computer hardware Standard Performance Evaluation Corporation Benchmark Ubuntu Computer performance CPU cache Computing SPECint Computer architecture
427	Marvell_Logo_PMSblack_noR Add to Reading List Source URL: www.marvell.com Language: English - Date: 2015-02-23 14:12:27 Computing Tegra PCI Express Serial ATA Marvell Technology Group ARM Cortex-A9 MPCore CPU cache Calxeda Computer hardware Computer architecture ARM architecture
428	SPEC CINT2006 Result CopyrightStandard Performance Evaluation Corporation aws -- Add to Reading List Source URL: s3.amazonaws.com Language: English - Date: 2014-11-13 04:15:03 Computer hardware Evaluation Standard Performance Evaluation Corporation Benchmark Ubuntu Computer performance CPU cache Intel C++ Compiler Xeon Computing SPECint Computer architecture
429	SPEC CINT2006 Result CopyrightStandard Performance Evaluation Corporation rackspace -- Add to Reading List Source URL: s3.amazonaws.com Language: English - Date: 2015-03-24 09:50:06 Computer hardware Standard Performance Evaluation Corporation Rackspace CPU cache Benchmark Xeon Computing SPECint Evaluation
430	Multi-threaded Performance Pitfalls 1 License Copyright © 2008 Ciaran McHale. Permission is hereby granted, free of charge, to any person obtaining a copy of this Add to Reading List Source URL: www.ciaranmchale.com Language: English - Date: 2008-05-17 08:17:29 Microprocessors Parallel computing Threads Central processing unit Computer memory Scalability Multi-core processor CPU cache Lock Computing Concurrent computing Computer hardware

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